Capacitive sensing

ABSTRACT

A capacitive sensing system includes a controller, a node connected to one side of a capacitance, the controller configured to measure the capacitance by measuring a time for a voltage across the capacitance to reach a predetermined reference voltage, a noise measurement circuit configured to measure electrical noise on the node, and the controller receiving the measurement of noise from the noise measurement circuit.

This application claims the benefit of U.S. Provisional Application No.61/770,116 filed Feb. 27, 2013, which is hereby incorporated byreference. This application is related to co-pending application [TIdocket number 74396] entitled “Capacitive Sensing”, filed on the sameday as this application, with the same inventorship and same assignee asthis application.

BACKGROUND

Capacitive sensing measures a capacitance resulting from two or moreconductive surfaces separated by a dielectric. Capacitive sensing iscommonly used to detect a change in capacitance resulting from theproximity of a human hand, a touch of a human finger, or a touch of aconductive stylus. Capacitive sensing is commonly used for humaninterfacing with electronic systems, for example; mobile phones, tabletcomputers, electronic games, electronic instruments, appliances,automotive systems, and industrial systems.

There are many alternative methods for capacitive sensing. For example,a capacitance may be measured by using the capacitance in an oscillatorand measuring the frequency of oscillation. Alternatively, a capacitancemay be measured by measuring the attenuation of an AC signal.Alternatively, a capacitance can be measured by measuring the timerequired to charge the capacitance through a known resistance. Eachalternative measurement method has inherent advantages, limitations andtradeoffs involving accuracy, cost, response-time, and so forth. Ingeneral, capacitive measurement circuits are affected by temperature,humidity, and electrical noise. There is an ongoing need for improvedcapacitive sensing.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a block diagram schematic of an example capacitive sensingsystem.

FIG. 1B is a timing diagram for a voltage waveform in the capacitivesensing system of FIG. 1A.

FIG. 2A is a block diagram schematic of an example alternativeembodiment of the capacitive sensing system of FIG. 1A.

FIG. 2B is a timing diagram for an example voltage waveform in thecapacitive sensing system of FIG. 2A.

FIG. 2C is a timing diagram for an alternative example voltage waveformin the capacitive sensing system of FIG. 2A.

FIG. 2D is a timing diagram for an alternative example voltage waveformin the capacitive sensing system of FIG. 2A.

FIG. 3A is a block diagram schematic of an example embodiment of a noisedetection circuit in the system of FIG. 2A.

FIG. 3B is a block diagram schematic of an example embodiment of analternative noise detection circuit in the system of FIG. 2A.

FIG. 4A is a block diagram of an alternative example embodiment of thecapacitive sensing systems of FIGS. 1A and 2A.

FIG. 4B is a timing diagram for an example voltage waveform in thecapacitive sensing system of FIG. 4A.

FIG. 5 is a flow chart illustrating an example embodiment of a methodfor capacitive sensing.

DETAILED DESCRIPTION

FIG. 1A is a simplified block diagram of an example system 100 forillustrating some basic principles for one particular method forcapacitive sensing. In the example of FIG. 1, a change in capacitance ismeasured by measuring the time required to charge or discharge thecapacitance. In FIG. 1, a conductive capacitive plate 102 is separatedfrom electrical ground by a dielectric 104. The dielectric 104 may be,for example, glass or air. An object 106 (for example, a human, depictedby an unknown variable resistance) provides a conductive path from thedielectric 104 to ground. There is an effective variable capacitanceC_(t) formed by the conductive plate 102, the dielectric 104, and theobject 106. N₁ designates the node connecting the conductive plate 102to the remaining circuitry. A switch 108 couples node N₁ to a voltage Vor to ground. A capacitance C may be, for example, the total linecapacitance resulting from all conductive traces connected to node N₁.Likewise, a resistance R may be the total resistance between the sourceof the voltage V and node N₁ (for example, the resistance of conductivetraces and the resistance of switch 108).

The switch 108 is controlled by a timer/controller 112. When the switch108 switches to the voltage V, the parallel capacitances (C and C_(t))start charging. A comparator 110 compares the voltage at node N₁ to ahigh reference voltage VREF_(HI) and to a low reference voltageVREF_(LO). The timer/controller 112 measures the time from the momentthat the switch 108 switches to the voltage V until the voltage at nodeN₁ equals the high reference voltage VREF_(HI). When the comparator 110switches states, the timer/controller causes the switch 108 to switch toground and the combined capacitances (C and C_(t)) start discharging.If, for example, a person (106) is touching the dielectric 104 (or justin proximity to the conductive plate 102), then the effectivecapacitance C_(t) is relatively large, and the parallel combination ofcapacitances (C and C_(t)) charges relatively slowly. If there is noobject 106 present, then the effective capacitance C_(t) is relativelysmall, and the parallel combination of capacitances (C and C_(t))charges relatively rapidly.

FIG. 1B illustrates an example waveform at node N₁. At time t₀ thetimer/controller 112 causes switch 108 to switch to the voltage V andthe capacitances (C and C_(t)) chart charging. At time t₁, the voltageat node N₁ reaches the high reference voltage VREF_(HI) and thecomparator 110 switches states. Also at time t₁, the timer/controller112 causes switch 108 to switch to ground and the capacitances (C andC_(t)) start to discharge. At time t₂, the voltage at node N₁ reachesthe low reference voltage VREF_(LO) and the timer/controller 112 startsanother timing period (causes switch 108 to switch to voltage V).

The system 100 is subject to numerous accuracy limitations. First,electrical noise on node N₁ can affect when the comparator 110 switchesstates. Node N₁ may be affected by both radiated and conductedelectrical noise. The conductive plate 102 may receive electrical noisefrom unintended electric fields and node N₁ may receive noise coupledfrom other electrical traces. In addition, node N₁ may be affected byelectrical noise on the power supply lines and on the ground lines. Ifcapacitive measurements are made periodically, then a particular concernis periodic noise having the same period as the measurements. Second, ifthe timer 112 is a digital counter counting clock pulses (CLK) thenthere is some inherent inaccuracy (resolution) in the digitalmeasurement of time. Third, the resistance R and the capacitances C andC_(t) may vary with temperature and humidity.

As illustrated in the example of FIG. 1B, the rate of change of thevoltage at node N₁ slows as the voltage at node N₁ increases towards thevoltage V. If the high reference voltage VREF_(HI) is close to thevoltage V, then there is a relatively long time during which the voltageat node N₁ is close to the high reference voltage VREF_(HI). Likewise,if the low reference voltage VREF_(LO) is close to ground, then there isa relatively long time during which the voltage at node N1 is close tothe low reference voltage VREF_(LO). During the periods of time when thevoltage at node N1 is close to one of the reference voltages (VREF_(HI),VREF_(LO)), a small amount of noise can cause the comparator 110 toswitch states at an inappropriate time (or to not switch states at theappropriate time). One way to improve noise immunity for the system offigure 100 is to set the reference voltages (VREF_(HI), VREF_(LO)) atlevels where the slope of the voltage at node N₁ is relatively high. Forexample, if VREF_(LO) is set to 0.2*V and if VREF_(HI) is set to 0.8*V,then the noise must be at least 0.2*V to cause the comparator 110 toswitch states at an inappropriate time. These thresholds are depicted inFIG. 1B by VREF_(LO)′ and VREF_(H1)′.

For the example of FIG. 1A, the timer/controller 112 may measure thetime for node N₁ to charge and/or discharge to the reference voltages(VREF_(HI), VREF_(LO)). Alternatively, the timer/controller 112 maymeasure the number of charge/discharge cycles that occur during a fixedperiod of time.

FIGS. 2A and 4A illustrate example systems with several improvements tothe system 100 in FIG. 1A. One improvement is that at least one constantcurrent source is used to charge and/or discharge the capacitances (Cand C_(t)). This causes the capacitances to charge and/or dischargelinearly instead of charging and discharging with a decreasing slope.Linear charging and discharging reduces the time that the input to thecomparator 110 is close to one of the reference voltage thresholds(VREF_(HI), VREF_(LO)), and therefore reduces the time window in whichthe comparator 110 is sensitive to noise. In addition, a current sourcemay overdrive some noise on node N₁. A second improvement is that themeasurements may be controlled to be a-periodic even when thecapacitance (parallel C and C_(t)) is constant. This reduces the effectsof periodic noise. One method for making the measurements a-periodic isillustrated in FIG. 2D and a second method for making the measurementsa-periodic is illustrated in FIGS. 4A and 4B. A third improvement isthat noise on node N₁ may be measured to enable the system to compensatefor noise, and/or to avoid measurements when the noise is too high,and/or to reject measurements that may have been subjected to unusualbursts of noise. A fourth improvement is to reject measurements that lieoutside expected limits.

In FIG. 2A, elements having the same reference numbers as in FIG. 1A areall as described in conjunction with FIG. 1A. In the example system 200of FIG. 2A, there are two current sources 202 and 204. At any giventime, at most one of the current sources 202 and 204 is coupled to nodeN₁. As discussed in conjunction with FIGS. 2C and 2D, one current source202 or 204 may be optional.

FIG. 2B illustrates an example waveform for node N₁ in FIG. 2A. At timet₀, the timer/controller 112 causes switch 108 to switch to currentsource 202 and the capacitances (C and C_(t)) start linearly charging.At time t₁, the voltage at node N₁ reaches the high reference voltageVREF_(HI) and the comparator 110 switches states. Also at time t₁, thetimer/controller 112 causes switch 108 to switch to current source 204and the capacitances (C and C_(t)) start to linearly discharge. At timet₂, the voltage at node N₁ reaches the low reference voltage VREF_(LO)and the timer/controller 112 starts another timing period (causes switch108 to switch to current source 202). Note that linear charging anddischarging reduces the time that the input to the comparator 110 isclose to one of the reference voltage thresholds (VREF_(HI), VREF_(LO)),and therefore reduces the time window in which the comparator 110 issensitive to noise.

FIG. 2C illustrates an example waveform for node N₁ for an alternativeembodiment of the system 200 of FIG. 2A. For FIG. 2C, assume there is nocurrent source 204 and instead, switch 108 couples node N₁ to currentsource 202 or to ground. For FIG. 2C, also assume that thetimer/controller 112 determines the time at which each new timing periodbegins independent of when the voltage at node N1 falls to the lowreference voltage VREF_(LO). At time t₀, the timer/controller 112 causesswitch 108 to switch to current source 202 and the capacitances (C andC_(t)) start linearly charging. At time t₁, the voltage at node N₁reaches the high reference voltage VREF_(HI) and the comparator 110switches states. Also at time t₁, the timer/controller 112 causes switch108 to switch to ground and the capacitances (C and C_(t)) start todischarge. At time t₂ the timer/controller 112 starts another timingperiod (causes switch 108 to switch to current source 202).

The voltage on node N₁ in FIG. 2A as depicted in FIG. 2C may besusceptible to noise having the same timing. In the example of FIG. 2C,the measurement time period from t₁ to t₂ is determined by thetimer/controller 112. This measurement time period from t₁ to t₂ may berandomized by the timer/controller 112 to cause the time period forcapacitance measurements to vary even when the capacitance (parallel Cand C_(t)) is constant. For example, the timer controller 112 maygenerate a pseudo-random time period for the time from t₁ to t₂.Alternatively, the timer controller 112 may pseudo-randomly choose fromtwo or more predetermined time periods. An example a-periodic waveformis illustrated in FIG. 2D. In FIG. 2D, the time period from t₁ to t₂ isnot equal to the time period from t₃ to t₄. Note that in the examples ofFIGS. 2C and 2D, charging is linear but discharging is non-linear(current source 202 but not current source 204). Alternatively, thesystem 200 may be configured so that discharging is linear and chargingis non-linear (current source 204 but not current source 202) and thetimer/controller 112 may vary the charging times. Alternatively, bothcharging and discharging may be linear or non-linear, and thetimer/controller 112 may vary either the charging time period or thedischarging time period.

The system 200 in FIG. 2A includes a noise measurement circuit 206. FIG.3A illustrates additional detail for an example embodiment of the noisemeasurement circuit 206 in FIG. 2A. Only part of FIG. 2A is duplicatedin FIG. 3A to facilitate illustration and discussion. In the example ofFIG. 3A, the switch 108 is coupled to a rectifier circuit 300, followedby an integrator 302, followed by an analog-to-digital converter (A/D)304. The output of the A/D 304 is read by the timer/controller 112. Themeasurement circuit 206 may optionally be capacitively coupled(capacitor C_(C)). Assuming that resistance R (trace resistance) issmall, the circuit of FIG. 3A effectively measures noise on node N₁ andintegrates the noise over time. The A/D 304 then provides a digitalmeasure of that noise to the timer/controller 112. If the circuit ofFIG. 3A is capacitively coupled (capacitor C_(C)), then the circuit ofFIG. 3A measures AC noise, and may be used whether the switch 108 isswitched or not-switched to one of the current sources (202, 204).

FIG. 3B illustrates additional detail for an alternative exampleembodiment of the noise measurement circuit 206 in FIG. 2A. Only part ofFIG. 2A is duplicated in FIG. 3B to facilitate illustration anddiscussion. In the example of FIG. 3B, when the switch 108 is switchedto current source 202, a known capacitance C₂ charges through a knownresistance R₂. An A/D 306 measures the voltage on capacitance C₂ after aknown period of time and the output of the A/D 306 is read by thetimer/controller 112. Assuming that resistance R (trace resistance) issmall relative to resistance R₂, the circuit of FIG. 3A effectivelymeasures noise on node N₁. With calibration, the expected voltage oncapacitance C₂ after the known period of time is known. If the actualvoltage is significantly different than the expected voltage, thedifference is assumed to be caused by noise.

For either example of noise measurement circuit 206, the noisemeasurement may be used change at least one capacitance measurementparameter. For example, the system 200 may determine that the noise istoo great to initiate a capacitance measurement and the capacitancemeasurement may be deferred. Alternatively, the noise measurement may beused to determine whether a capacitance measurement is valid socapacitance measurements may be rejected if capacitance measurements aresubject to excess noise. Alternatively, the reference voltages(VREF_(HI), VREF_(LO)) may be adjusted based on noise level. Forexample, VREF_(HI) may be adjusted closer to the supply voltage andVREF_(LO) may be adjusted closer to ground if the noise level isrelatively low. Alternatively, the timer/controller 112 may have anexpected range of charging time periods (for example, FIG. 2C, t₀ to t₁and t₂-t₃) and the timer/controller 112 may reject measurements having acharging time period outside the expected range. The expected range maybe reduced if the noise measurement circuit 206 indicates that noise isrelatively low.

FIG. 4A illustrates an example embodiment of a system 400 that is analternative embodiment of the system 200 of FIG. 2A, illustrating analternative way of ensuring that the time period for capacitancemeasurements is variable even when the capacitance (parallel C andC_(t)) is constant. In FIG. 4A, elements having the same referencenumbers as in FIGS. 1A and 2A are all as described in conjunction withFIGS. 1A and 2A. In the example of FIG. 4A, there are at least twocurrent sources (402, 404) that may be coupled to node N₁ by switches(406, 408) controlled by the timer/controller 112. In the example ofFIG. 4A, node N₁ is discharged by a switch 410 instead of by a currentsource to ground, but a current source to ground may optionally be used.The currents sourced by current sources 402 and 404 are not equal.Accordingly, the time periods required for node N₁ to charge to the highreference voltage VREF_(HI) are not equal because the currents providedby the different current sources are not equal. The timer/controller mayselect switches 406 and 408 in a pseudo-random sequence so that thevoltage waveform on node N₁ is a-periodic even when the capacitance(parallel C and C_(t)) is constant. Alternatively, the system 400 may beconfigured so that a plurality of current sources are used to discharge,and the time periods required for node N₁ to discharge to the lowreference voltage VREF_(LO) are made to be unequal.

FIG. 4B illustrates an example waveform on node N₁ of FIG. 4A. At timet₀, switch 406 switches current source 402 to node N₁ and thecapacitances (C and C_(t)) linearly charge until the voltage at node N₁equals the high reference voltage VREF_(HI). At time t₁, switch 410 isclosed to discharge the capacitances. At time t₂, switch 410 opens andswitch 408 closes to switch current source 404 to node N₁ and thecapacitances (C and C_(t)) linearly charge until the voltage at node N₁equals the high reference voltage VREF_(HI). Note that since currentsource 402 is not identical to current source 404, the time period fromt₀ to t₁ is different than the time period from t₂ to t₃. Switches 406and 408 are closed in a pseudo-random sequence so that the resultingvoltage waveform on node N₁ is a-periodic.

FIG. 5 illustrates an example method 500 for capacitive sensing. Note,the particular order of steps as illustrated does not mean that thesteps must be performed in the illustrated order, and some steps may beperformed simultaneously. At step 502 a voltage at a node is changed. Atstep 504 a controller measures a capacitance at the node by measuring atime required for the node voltage to equal a predetermined threshold.At step 506 a noise measurement circuit measures electrical noise on thenode. At step 508 the controller changes at least one capacitancemeasurement parameter in response to the measured noise.

Note that illustrating the timer/controller 112 as one functional unitis only to facilitate illustration and discussion, and the timing andcontrolling functions may be implemented by separate functional units.Likewise, illustration of the comparator 110, the timer/controller 112,the noise measurement circuit 206, the A/D 304, and the A/D 306 asseparate functional units is only to facilitate illustration anddiscussion, and the timer/controller 112 may include any or all of theseparately labeled functions.

While illustrative and presently preferred embodiments of the inventionhave been described in detail herein, it is to be understood that theinventive concepts may be otherwise variously embodied and employed andthat the appended claims are intended to be construed to include suchvariations except insofar as limited by the prior art.

What is claimed is:
 1. A capacitive sensing system, comprising: acontroller; a node connected to one side of a capacitance; thecontroller configured to measure the capacitance by measuring a time fora voltage across the capacitance to reach a predetermined referencevoltage; a noise measurement circuit configured to measure electricalnoise on the node; and the controller receiving the measurement of noisefrom the noise measurement circuit.
 2. The capacitive sensing system ofclaim 1, the noise measurement circuit comprising an integrator thatintegrates electrical noise on the node.
 3. The capacitive sensingsystem of claim 1, the noise measurement circuit comprising a capacitorcoupled to the node and an analog-to-digital converter measuring thevoltage across the capacitor.
 4. The capacitive sensing system of claim1, where the controller is adapted to adjust at least one measurementparameter in response to the output of the noise measurement circuit. 5.The capacitive sensing system of claim 4, where the controller isadapted to defer making a capacitance measurement in response to theoutput of the noise measurement circuit.
 6. The capacitive sensingsystem of claim 4, where the controller is adapted to reject acapacitive measurement in response to the output of the noisemeasurement circuit.
 7. The capacitive sensing system of claim 4, wherethe controller is adapted to adjust a voltage threshold in response tothe output of the noise measurement circuit.
 8. The capacitive sensingsystem of claim 4, where the controller is adapted to adjust a timingrange in response to the output of the noise measurement circuit.
 9. Thecapacitive sensing system of claim 1, where the controller causes thetime period for capacitance measurements to vary even when thecapacitance is constant.
 10. The capacitive sensing system of claim 9,where the controller causes the time period for capacitance measurementsto vary by generating a random time period for charging the node. 11.The capacitive sensing system of claim 9, where the controller causesthe time period for capacitance measurements to vary by generating arandom time period for discharging the node.
 12. The capacitive sensingsystem of claim 9, where the controller causes the time period forcapacitance measurements to vary by randomly choosing from two or morepredetermined times for charging the node.
 13. The capacitive sensingsystem of claim 9, where the controller causes the time period forcapacitance measurements to vary by randomly choosing from two or morepredetermined times for discharging the node.
 14. The capacitive sensingsystem of claim 9, further comprising: at least two current sources forcharging the node; and where the controller causes the time period forcapacitance measurements to vary by randomly selecting among the atleast two current sources to charge the node.
 15. The capacitive sensingsystem of claim 9, further comprising: at least two current sources fordischarging the node; and where the controller causes the time periodfor capacitance measurements to vary by randomly selecting among the atleast two current sources to discharge the node.
 16. A method forcapacitive sensing, comprising: changing a voltage at a node; measuring,by a controller, a capacitance at the node by measuring a time requiredfor the node voltage to reach a predetermined threshold; measuring, by anoise measurement circuit, electrical noise on the node; and changing,by the controller, at least one capacitance measurement parameter inresponse to the measured noise.
 17. The method for capacitive sensing ofclaim 16, the step of changing at least one capacitance measurementparameter further comprising deferring making a capacitance measurementin response to the output of the noise measurement circuit.
 18. Themethod for capacitive sensing of claim 16, the step of changing at leastone capacitance measurement parameter further comprising rejecting acapacitance measurement in response to the output of the noisemeasurement circuit.
 19. The method for capacitive sensing of claim 16,the step of changing at least one capacitance measurement parameterfurther comprising adjusting a voltage threshold in response to theoutput of the noise measurement circuit.
 20. The method for capacitivesensing of claim 16, further comprising changing, by the controller, atleast one measurement time period to make capacitance measurementsa-periodic.